1. Field of the Invention
The present invention relates to a data processor, and more specifically to an instruction control system for use in a data processor for controlling re-execution of a given instruction.
2. Description of related art
Central processors, which have adopted the conventional instruction control system, ordinarily comprise a instruction prefetch unit for prefetching instructions through a bus interface from an external bus and accumulating the prefetched instructions so as to form an instruction queue. This instruction prefetch unit is coupled to a instruction decoder so as to supply a code of instruction in response to a request from the decoder. The instruction decoder decodes the added instruction supplied from the instruction prefetch unit, and outputs control information to an instruction execution unit. Further, the execution unit calculates an effective address for a memory operand so as to output it to the bus interface. Thus, the instruction execution unit executes a given operation on the basis of the control information supplied from the instruction decoder. On the other hand, the bus interface executes access to the external memory on the basis of the address supplied from the instruction decoder and also executes a prefetch of an instruction for the instruction prefetch unit.
A central processor having the above mentioned construction is generally operated to fetch an instruction, to decode the instruction, to calculate an address for a memory operand and to read/write to the calculated address. However, if a so called "page fault" occurs at the time of memory access, the processor replaces a page by another page with a unit of one page, and re-executes the operation from a head of the given unit of instruction. For example, in the case of an IN instruction which is one typical example of input/output instructions, the central processor decodes the IN instruction and executes a reading of an input/output address indicated by the instruction so as to write the read data at a predetermined address. If a page fault occurs in the course of the above operation, the central processor carries out a page replacement, and thereafter, re-executes from the head of the instruction.
As mentioned above, when the page fault has occurred, the instruction is re-executed from its head after the replacement of the page. However, in the case of input/output instructions, the data to be read out at the time of re-execution has often become inaccurate. For example, some peripheral pieces of equipment assigned with input/output addresses have often changed the content of data after it had been read in the first place. In this case, it is no longer possible to obtain correct data from the peripheral equipment at the time of re-execution.
In order to avoid the above mentioned problem, it has been necessary to elaborate such a program as to designate an address which will not cause a page fault. However, such a program is inevitably accompanied with various restrictions in programming.